This invention is generally related to integrated circuit (IC) signal timing circuitry and, more particularly, to a method of delaying signals through an elastic store for delay times incremented through phase control of the clocking signals.
An elastic store is a circuit often used in a receiver to acquire asynchronous input data, or to collect data from sources with unpredictable transmission delays. The elastic store can also be used to combine multiplexed data sources, or in the receiver channel of a cross-point switch. The elastic store receives data at uncertain clock rates and converts it to the receiver clock rate. Conventionally, the elastic store accepts data at a write (WR) clock rate, and supplies it at the read (RD) clock rate. Delay is added to the system by adjusting the number of clock cycles between when data is written, and when it is read.
Conventional elastic store circuits provide a delay of at least one clock cycle. These circuits are useful if large delays are required between the input and output data. However, problems arise in using elastic stores to create a delay of less than a clock cycle. Neither are conventional elastic stores useful if a delay equal to a non-integer value of a clock cycle is required, for example, a delay of 1.5 clock cycles. It is possible to add delay circuitry to the input or output data lines of the elastic store to achieve delays that are not an integer value of a clock cycle. However, keeping such delay circuitry synchronously aligned with the WR and RD clocks of the elastic store is a problem. Further, such delay circuitry is not readily available for high speed waveforms.
In co-pending patent application Ser. No. 09/420,983, entitledxe2x80x9cELASTIC STORE CIRCUIT WITH VERNIER CLOCK DELAY,xe2x80x9d filed on Oct. 20, 1999 still pending, Anderson et al. disclose a system of adding a vernier controlled delay to a reference clock, which results in elastic store delays of much less than a read or write clock cycle. The system delays the reference clock so that small delay increments can be added between the WR and RD clocks.
It would be advantageous if an elastic store could delay data for periods of time that are less than the WR and RD clock cycles to provide precise control over the timing of signals.
It would be advantageous if delays of less than a WR/RD clock cycle could be made programmable and repeatable.
It would be advantageous if elastic store delays of less than a read or write clock cycle could be controlled with the accuracy of phase-locking circuitry.
It would be advantageous if non-integer clock cycle delays could be maintained in a synchronous relationship to the WR and RD clocks.
It would be advantageous if an elastic store had the capacity to delay data signals for periods of time greater than a WR/RD clock cycle, simultaneously with the capacity to make adjustments that are in increments smaller than the period of a WR/RD clock.
Accordingly, an elastic store with programmable phase delay is provided. The elastic store comprises a static phase offset circuit to accept a reference clock, and a phase delay control signal. The static phase offset circuit has an output to provide a read (RD) clock, that is phase delayed with respect a write (WR) clock. The static phase offset circuit delays the RD clock in response to the phase delay control signal.
A first in/first out (FIFO) circuit has inputs to receive data input, the WR clock, and the RD clock. The FIFO output provides the data input at the FIFO output, delayed by a first delay, which corresponds to the difference between the phases of the WR and RD clocks. In this manner, the input signals are delayed in response to the clock signals.
The static phase offset circuit includes sub-circuits. A phase bias circuit accepts the frequency divided RD clock, called the null-phased reference compare reference signal. The phase bias circuit also accepts a phase delay control signal. An output provides a phase-biased reference compare signal. That is, the phase bias circuit cancels out, or offsets the phase bias associated with the phase-nulled references signal. The loop is locked with the RD clock having a phase offset with respect to the reference clock driving the WR clock.
A first clock synthesizer unit (CSU) receives the phase-biased reference compare signal, and outputs the RD clock. The first CSU varies the RD clock in response to the phase bias added to the reference clock. The first CSU includes sub-circuits. A first phase detector accepts the reference clock and the phase-biased reference compare signal, and provides a frequency source voltage. A frequency source accepts the frequency source voltage, and provides the RD clock. The elastic store also includes a second CSU to receive the reference clock, and provide the WR clock, phase-locked to the reference clock.
A method for precisely controlling the phase of input data in a data transfer is also provided comprising the steps of:
a) generating a reference clock;
b) generating a null-phased reference compare signal in response by offsetting the phase of the reference clock;
c) generating a write (WR) clock, phase-locked to the reference clock;
d) generating a read (RD) clock, statically delayed in phase with respect the WR clock, and phase-locked to the null-phased reference compare signal;
e) writing input data at the WR clock rate; and
d) reading the input data at the RD clock rate, whereby an elastic store with a first delay corresponding to the phase difference of the WR and RD clocks is created.